This invention relates to semiconductor memory devices and more particularly to a dynamic memory device of the type having an array of rows and columns of memory cells.
The most widely used semiconductor memory devices at present are large scale arrays of one-transistor dynamic memory cells of the type described in U.S. Pat. No. 3,940,747, issued Feb. 24, 1976, to Kuo and Kitagawa, assigned to Texas Instruments. Higher density versions of these memory systems are shown in Electronics, May 13, 1976, pp. 81-86. These high density devices use one-transistor dynamic memory cells which have the advantage of very small size, and thus low cost. Row addresses and column addresses are separately applied to row and column decoders which select on row and one column for access, with the remaining rows and columns being non-activated. In some situations, it has been found that the non-selected column decoder outputs can have unwanted voltages trapped thereon, as there is no path for discharge. This condition can result in loss of data or storing of erroneous data.
It is the object of this invention to provide an improved semiconductor memory device of the type having an array of rows and columns of dynamic memory cells, and in particular with provision for avoiding trapping of unwanted voltages on nodes in the decode circuitry.